With receiver circuits used in information processing units, large scale integrated circuits (LSI), and the like, clock data recovery (CDR) by which a value (data) and a clock signal are reproduced from a transmitted data signal is performed. With the CDR, in order to make a data decision (sampling) at a proper timing, the difference in phase between a clock signal for data decision and a data signal is detected and a phase of the clock signal is adjusted.
Formerly, a CDR circuit which performs two sampling operations per symbol (which may also be referred to as a unit interval (UI)) of a data signal (hereinafter referred to as 2× sampling) has been known. With this CDR circuit, a second clock signal other than a clock signal for data decision is used for detecting an edge portion (zero-crossing point) of a data signal. Furthermore, on the basis of an amplitude level of the data signal at a timing synchronized with the second clock signal, adjustment is made so that the timing will be locked at the zero-crossing point. The clock signal for data decision is adjusted so that its phase will deviate 0.5 UIs from that of the above second clock signal.
With a CDR circuit which performs 2× sampling, however, two sampling operations are performed per symbol. As a result, power consumption increases. A CDR circuit which performs one sampling operation per symbol (hereinafter referred to as 1× sampling) is known as a CDR circuit which reduces power consumption based on a clock signal. With a CDR circuit which performs 1× sampling, a data decision circuit (including, for example, an equalizer) decides a value of a data signal for each symbol at a timing synchronized with a clock signal. Furthermore, on the basis of an amplitude level of the data signal at a timing at which data corresponding to two symbols is decided, a difference in phase is detected and a phase of the clock signal is adjusted.
By the way, a receiver circuit may include an eye monitoring function for evaluating receiving characteristics within the circuit. The eye monitoring function is the function of detecting how a bit error rate (BER) changes when a phase of a clock signal and a threshold for data decision are changed. If the eye monitoring function is applied to a CDR circuit which performs 2× sampling, an offset value is added to a phase of a clock signal for data decision.
In view of a situation in which the operating speeds of circuits and elements are approaching the limits, adoption of a multilevel transmission technology, such as Pulse Amplitude Modulation 4 (PAM-4), is proposed in the latest communication standard as a technology for improving a data rate without increasing an operating speed.
See, for example, Japanese Laid-open Patent Publication No. 2015-192200.
With a receiver circuit including a CDR circuit which performs 1× sampling, the following problem arises. If an offset value is added to a phase of a clock signal used both for data decision and for phase difference detection, then the offset value is canceled by a phase adjustment function. As a result, an eye monitoring function is not realized. In order to realize an eye monitoring function, a clock signal whose phase is adjustable by an offset value and a data decision circuit are added and a data decision result for eye monitoring is outputted to the data decision circuit at a timing synchronized with the clock signal. In that case, however, there arises a problem that power consumption increases. If a multilevel transmission technology is used, this problem becomes more serious as the scale of a data decision circuit increases.